Before the advent of electronic timepieces, the most generally used method of correcting the time information of a wristwatch or other small timepiece was that of rotation of a crown. This method is therefore very familiar to many users, and has various other advantages. Various types of electronic timepieces have also been proposed in recent years, in which correction of current time, and in some cases also of the alarm time, is performed by rotation of a crown which is linked to a switch mechanism. Rotation of the crown causes the switch mechanism to generate a train of correction pulses, which are applied to the timekeeping counter circuits to correct the contents thereof, or to set in a desired alarm time. The rate at which these correction pulses are generated is determined by the rate at which the user rotates the crown, and various circuits have been devised whereby a large number of correction pulses can be generated for each rotation of the crown, so that the user can rapidly and conveniently perform time correction. In recent years, also, electronic timepieces have been designed in which a central processing unit (generally abbreviated to CPU) is utilized to perform various functions in the timepiece, including the timekeeping computations, etc. Use of a CPU provides a number of advantages, from a manufacturing viewpoint. Since the operation of the CPU, and hence the overall operation of the timepiece, is controlled by the CPU operating program, changes in the timepiece operation can be easily performed by changes in that operating program. Such changes are facilitated by the fact that the operating program of the CPU is generally stored in a read-only memory (generally abbreviated to ROM) integrated circuit, so that the operating program can be changed by modifying the contents of the ROM, by such methods as the memory mask technique. Thus, for the above reasons, it is possible to manufacture a wide range of timepieces having different functions and modes of operation, incorporating a single CPU integrated circuit of standardized design in each timepiece, with the operating program suitably modified for the particular type of timepiece. With conventional methods of electronic timepiece manufacture, in which randomly arranged logic is designed individually for each particular type of electronic timepiece integrated circuit, any change in the functions of a timepiece generally necessitates a complete redesign of the integrated circuit. Use of a CPU, therefore, enables design changes in electronic timepiece manufacture to be performed in a much more flexible and economical manner than is possible with previous methods of circuit implementation. However, the use of a CPU in an electronic timepiece equipped with a crown, for input of correction signal pulses, has hitherto involved various difficulties. These are basically due to the fact that the correction signal pulses from the switch mechanism coupled to the timepiece crown are generated as a serial pulse train, at relatively high frequency, whereas the CPU is limited in its capability for processing such high speed serial data. This is because the operating clock signal of the CPU, i.e. the basic timing clock of the CPU operation, is usually derived from the output of the quartz crystal oscillator which serves as the standard frequency signal source of the timepiece, and the CPU clock signal is therefore generally at half the frequency of the crystal oscillator output signal. Thus, since the quartz crystal oscillator circuit of the timepiece generally operates at a frequency of the order of 32 kHz, the maximum clock signal frequency available for operating the CPU is of the order of 16 kHz, i.e. the clock signal period is about 60 microseconds. It is a feature of a CPU circuit that its power consumption, when actually in operation, is extremely high, by comparison with the normal levels of power consumption of electronic timepiece circuitry. It is therefore usual to arrange that the CPU is normally held in a non-operative condition until some data processing operation is actually required, for example when time data updating is to be performed, or when input of a correction signal occurs. In the latter case, it is necessary for the CPU to first recognize the fact that some switch actuation has occurred, thereby generating the correction signal, before actual processing of the correction signal can begin. This recognition processing can take several hundreds of microseconds, due to the low clock signal frequency of the CPU operation. Thereafter, the correction signal data must be processed. Thus, in the case of a high speed input of correction pulses produced by a switch mechanism actuated by rotation of a crown, the CPU may simply be too slow in operation to process the input signal.
In order to successfuly utilize a CPU in an electronic timepiece equipped with a crown actuated switch for generating a high frequency train of correction pulses, therefore, it is necessary to provide some means of overcoming the basic mismatch between the correction pulse signal input and the relatively slow, essentially parallel, operation of the CPU. It should be noted that the rate of input of correction pulses from a crown-operated switch mechanism is completely random with respect to time, so that if the correction signal input is applied directly to the CPU, the latter must judge each switch closure representing a correction pulse individually, before processing that pulse, i.e. before adding to or subtracting a quantity corresponding to that correction pulse from previously stored data.
With the present invention, the above disadvantages of combining a CPU with a crown-operated correction switch mechanism in an electronic timepiece are eliminated, by providing a counter as a type of temporary storage means, or buffer, between the correction signal source and the CPU input. The contents of this counter are monitored by a zero detection circuit, which activates the CPU to begin processing of input data from the crown switch only after actuation of the crown has begun, the data contents of the input counter circuit being then transferred, in parallel form, to the CPU. This process is repetitively performed while the crown is being rotated. In this way, the rate at which data is generated by the crown-actuated correction switch need not be limited by the operating speed of the CPU.